TWEPP 2022 AWARD
ALTIROC2 is the first full-scale 225-channel ASIC prototype designed for LGAD (low Gain Avalanche Diodes) readout, as part of the new ATLAS HGTD detector foreseen for the High Luminosity-LHC upgrade. The scientific goals require to detect charges as small as 2 fC with a 95% efficiency and to exhibit a 25 ps jitter for 10 fC input charge with less than 5 mW/channel. The 2x2 cm² chip was fabricated in CMOS 130nm in 2021 and on-going extensive characterisation results will be presented for the ASIC bump-bonded onto the LGAD detector, as well as preliminary results of TID and SEE tests.
The large increase of the particle flux at the high luminosity phase of the LHC (HL-LHC) with instantaneous luminosities up to L ≃ 7.5×10^34 cm^−2 s^-1 will have a severe impact on the ATLAS detector performance. Pile-up mitigation is one of the main challenges as 200 interactions per bunch crossing are expected on average. Providing a high-precision timing information to distinguish between collisions occurring close in space but well-separated in time, the new High Granularity Timing Detector (HGTD) will cover the forward region with pseudo-rapidity range from 2.4 to about 4.0.
Two double sided layers of silicon sensors will provide a precision timing information for minimum ionizing particles with a time resolution better than 70 ps per hit (i.e. 50 ps per track at the end of operational lifetime) in order to assign the particle to the correct vertex. Low Gain Avalanche Detectors (LGAD) technology was chosen as it provides an appropriate internal gain to reach large signal over noise ratio needed for excellent time resolution.
ALTIROC2 is the first full-scale 225-channel ASIC prototype designed in CMOS 130 nm. It is bump-bonded onto a 15 x 15 channel matrix of 1.3 mm x 1.3 mm x 50 µm pixel LGAD of the new ATLAS HGTD detector foreseen for the High Luminosity-LHC upgrade, where high radiation levels are expected (200 MRad and 2.5x 10^15 neq/cm2 fluence). The chip was received in October 2021 and is under test since then.
Each ASIC channel integrates a 1 GHz preamplifier followed by a large gain leading edge discriminator and two TDCs for Time-of-Arrival and Time-Over-Threshold measurements as well as a 35 µs depth memory. Zero suppression is done at pixel level. A luminosity measurement is also performed by the ASIC. Timing data and luminosity data are output at a rate up to 1.28 Gb/s to the DAQ. The front-end must detect charges as small as 2 fC with 95 % efficiency and must exhibit a jitter of 25 ps for 10 fC input charges while keeping a challenging power consumption of less than 4.5 mW per channel.
This talk will detail the ASIC front-end architecture, some critical design choices and measurements (voltage vs transimpedance preamp, noise, minimum charge threshold, jitter…) compared to simulations, as several chips are currently being tested by the HGTD collaboration since November 2021. Measurements obtained at system level with ASICs bump-bonded onto a sensor will also be shown.